rev.2.00, oct 06, 2005 page 1 of 7 hd74hc75 quad. bistable latches rej03d0550-0200 (previous ade-205-422) rev.2.00 oct 06, 2005 description this latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator units. information present at the data (d) input is transferred to the q output when the latch enable (le) is high. the q output will follow the data input as long as the enable remains high. when the enable goes low, the information that was present at the data input at the time the transition occurred is retained at the q output unit the enable is permitted to go high again. features ? high speed operation: t pd (d to q) = 12.5 ns typ (c l = 50 pf) ? high output current: fanout of 10 lsttl loads ? wide operating voltage: v cc = 2 to 6 v ? low input current: 1 a max ? low quiescent supply current: i cc (static) = 2 a max (ta = 25 c) ? ordering information part name package type package code (previous code) package abbreviation taping abbreviation (quantity) hd74hc75p dilp-16 pin prdp0016ae-b (dp-16fv) p ? hd74hc75fpel sop-16 pin (jeita) prsp0016dh-b (fp-16dav) fp el (2,000 pcs/reel) HD74HC75RPEL sop-16 pin (jedec) prsp0016dg-a (fp-16dnv) rp el (2,500 pcs/reel) note: please consult the sales office for the above package availability. function table inputs outputs data latch enable q q l h l h h h h l x l q 0 q 0 h : high level l : low level x : irrelevant q 0 , q 0 : output level before the indicated steady state input conditions were established.
hd74hc75 rev.2.00, oct 06, 2005 page 2 of 7 pin arrangement 1 2 3 4 5 6 7 8 q 0a d 0a d 1a le b v cc d 0b d 1b q 1b q 0a q 1a q 1a le a gnd q 0b q 0b q 1b 16 15 14 13 12 11 10 9 (top view) logic diagram (1/4) data q q latch enable absolute maximum ratings item symbol ratings unit supply voltage range v cc ?0.5 to 7.0 v input / output voltage vin, vout ?0.5 to v cc +0.5 v input / output diode current i ik , i ok 20 ma output current i o 25 ma v cc , gnd current i cc or i gnd 50 ma power dissipation p t 500 mw storage temperature tstg ?65 to +150 c note: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
hd74hc75 rev.2.00, oct 06, 2005 page 3 of 7 recommended operating conditions item symbol ratings unit conditions supply voltage v cc 2 to 6 v input / output voltage v in , v out 0 to v cc v operating temperature ta ?40 to 85 c 0 to 1000 v cc = 2.0 v 0 to 500 v cc = 4.5 v input rise / fall time *1 t r , t f 0 to 400 ns v cc = 6.0 v note: 1. this item guarantees maximum limit when one input switches. waveform: refer to test circuit of switching characteristics. electrical characteristics ta = 25 c ta = ?40 to+85 c item symbol v cc (v) min typ max min max unit test conditions 2.0 1.5 ? ? 1.5 ? 4.5 3.15 ? ? 3.15 ? v ih 6.0 4.2 ? ? 4.2 ? v 2.0 ? ? 0.5 ? 0.5 4.5 ? ? 1.35 ? 1.35 input voltage v il 6.0 ? ? 1.8 ? 1.8 v 2.0 1.9 2.0 ? 1.9 ? 4.5 4.4 4.5 ? 4.4 ? 6.0 5.9 6.0 ? 5.9 ? i oh = ?20 a 4.5 4.18 ? ? 4.13 ? i oh = ?4 ma v oh 6.0 5.68 ? ? 5.63 ? v vin = v ih or v il i oh = ?5.2 ma 2.0 ? 0.0 0.1 ? 0.1 4.5 ? 0.0 0.1 ? 0.1 6.0 ? 0.0 0.1 ? 0.1 i ol = 20 a 4.5 ? ? 0.26 ? 0.33 i ol = 4 ma output voltage v ol 6.0 ? ? 0.26 ? 0.33 v vin = v ih or v il i ol = 5.2 ma input current iin 6.0 ? ? 0.1 ? 1.0 a vin = v cc or gnd quiescent supply current i cc 6.0 ? ? 2.0 ? 20 a vin = v cc or gnd, iout = 0 a switching characteristics (c l = 50 pf, input t r = t f = 6 ns) ta = 25 c ta = ?40 to +85 c item symbol v cc (v) min typ max min max unit test conditions 2.0 ? ? 125 ? 155 4.5 ? 12 25 ? 31 6.0 ? ? 21 ? 26 ns data to q 2.0 ? ? 110 ? 140 4.5 ? 13 22 ? 28 6.0 ? ? 19 ? 24 ns data to q 2.0 ? ? 145 ? 180 4.5 ? 12 29 ? 36 6.0 ? ? 25 ? 31 ns latch enable to q 2.0 ? ? 125 ? 155 4.5 ? 13 25 ? 31 propagation delay time t plh , t phl 6.0 ? ? 21 ? 26 ns latch enable to q
hd74hc75 rev.2.00, oct 06, 2005 page 4 of 7 switching characteristics (c l = 50 pf, input t r = t f = 6 ns) ta = 25c ta = ?40 to +85c item symbol v cc (v) min typ max min max unit test conditions 2.0 100 ? ? 125 ? 4.5 20 4 ? 25 ? setup time t su 6.0 17 ? ? 21 ? ns data to latch enable 2.0 5 ? ? 5 ? 4.5 5 0 ? 5 ? hold time t h 6.0 5 ? ? 5 ? ns latch enable to data 2.0 80 ? ? 100 ? 4.5 16 5 ? 20 ? pulse width t w 6.0 14 ? ? 17 ? ns latch enable 2.0 ? ? 75 ? 95 4.5 ? 5 15 ? 19 output rise/fall time t tlh , t thl 6.0 ? ? 13 ? 16 ns input capacitance cin ? ? 5 10 ? 10 pf test circuit v cc latch enable v cc z out = 50 ? input data z out = 50 ? input c l = 50 pf output c l = 50 pf output q q note: c includes the probe and jig capacitance. l pulse generator pulse generator see function table
hd74hc75 rev.2.00, oct 06, 2005 page 5 of 7 waveforms 0 v v cc v oh latch enable q 50 % 10 % 90 % t r 50 % 50 % 10 % 90 % t tlh 10 % t thl 50 % 50 % t plh t phl v ol 0 v v cc 50 % 10 % 90 % t r 10 % t f 50 % 50 % d 90 % t h t su t h t su 90 % v oh q 10 % 90 % t tlh 10 % t thl 50 % 50 % t phl t plh v ol 90 % 10 % t f 90 % 50 % t w t w t w t w t phl t plh t phl t plh 1. input waveform: prr 1 mhz, zo = 50 ? , t r 6 ns, t f 6 ns note: ? waveform ? 1
hd74hc75 rev.2.00, oct 06, 2005 page 6 of 7 package dimensions 7.62 dp-16fv renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 19.2 6.3 5.06 mass[typ.] 1.05g a z b d e a b c e l 1 1 p 3 e 0.51 0.56 1.30 0.19 0.25 0.31 2.29 2.54 2.79 0 15 prdp0016ae-b p-dip16-6.3x19.2-2.54 20.32 7.4 0.40 0.48 1.12 2.54 1 p 1 3 1 8 16 9 e b a l a z e c e d b 0.89 ( ni/pd/au plating ) 0.635 0.15 1.27 5.80 6.20 0.40 0.34 p a 1 10.30 fp-16dnv renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 1.75 1.27 0.60 0.40 3.95 0.25 0.14 0.10 0.46 0.25 0.20 0.15 6.10 8 0 0.25 1.08 9.90 0.15g mass[typ.] 1 e 1 1 2 l z h y x c b a e d b c e e l a p-sop16-3.95x9.9-1.27 prsp0016dg-a index mark e 1 y xm p * 3 * 2 * 1 f 8 9 16 e h d a zb terminal cross section ( ni/pd/au plating ) p b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset.
hd74hc75 rev.2.00, oct 06, 2005 page 7 of 7 0.80 0.15 1.27 7.50 8.00 0.40 0.34 p a 1 10.5 fp-16dav renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 2.20 0.90 0.70 0.50 5.50 0.20 0.10 0.00 0.46 0.25 0.20 0.15 7.80 8 0 0.12 1.15 10.06 0.24g mass[typ.] 1 e 1 1 2 l z h y x c b a e d b c e l a p-sop16-5.5x10.06-1.27 prsp0016dh-b * 1 * 2 e 8 1 16 9 xm p * 3 y f index mark b d e h z a terminal cross section ( ni/pd/au plating ) p c b 1 1 detail f l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e
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